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Honored ContributorHPS SPI Master with more than 4 Slave Selects
Good afternoon, for a new hardware project we require an SPI interface from an Arria 10 SoC with more than 4 slave devices / slave selects. The Arria 10 SoC SPI Master Controller does only su...
Altera_ForumHonored Contributor
Honored ContributorA 4->16 decoder with the 4 CS lines as input will allow you to access to 16 slaves.
The 4 bits of the SER register are sent out (inverted) "as is" on the 4 chip selects lines SER register description: each bit in this register corresponds to a slave select line (spim_ss_x_n] from the spi master. when a bit in this register is set (1), the corresponding slave select line from the master is activated when a serial transfer begins. it should be noted that setting or clearing bits in this register have no effect on the corresponding slave select outputs until a transfer is started. before beginning a transfer, you should enable the bit in this register that corresponds to the slave device with which the master wants to communicate. when not operating in broadcast mode, only one bit in this field should be set.
