Okay a few principles first. The purpose of DMA is to speed up data transfers. Usually large data transfers. Because of this you should run the DMA controller, FIFO, and SDRAM all at the same clock. If you do not then SOPC builder will introduce clock arbitrator modules to cross between clock domains and that will kill any performance gains you would get from using the DMA controller.
Now 2.5MHz is dog slow. Are you sure the SDRAM can even run that slow? There has got to be a maximum tCK spec on that thing somewhere and I'll bet you're not meeting it.
About the FIFO, what type of FIFO is it? Single or Dual clock? What type of memory did you base it off of (M512, M4K, M-RAM)? Whatever it is, your HDL code should protect the FIFO so the contents don't get corrupted if you write to it while full or read from it while empty. Now if you want to hold the DMA controller off from reading the FIFO until there is data there to be read, you should use the Avalon waitrequest signal. Whenever this signal is asserted, the avalon master accessing the port (In this case the DMA controller) is forced to wait. Read the following document for reference:
http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (
http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)
As far as the DMA controller itself goes, you have full control over its behavior. If you want you can bypass the altera HAL functions and access the DMA controller's registers directly. This gives you direct control over how and when data gets transferred and you can read certain registers to determine when the transfer has finished.
Feel free to ask any further questions.
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