How to test SDRAM?

I think the phase shift for stability can only be found by doing exhaustive read/write tests on the SDRAM itself. If you are using an Altera dev kit, then there is a tested default value which should work fine.

For future enhancements, if it is available, the PLL can be reconfigured by software, and you can "tune" the PLL phase shift to achieve an optimum setting.

As for the management of program memory space and the heap stack, I do not see a boundary that disallow user from stepping over the very vulnerable memory space. It is up to the user to manage that flexibility.