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Does "the memory" include all of the following memory: FPGA Flash, FPGA EPCS, FPGA off-chip SRAM/SDRAM, and FPGA on-chip RAM?
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An Avalon master can write to any of the slaves (provided the conection is enabled in the SOPC builder). Writing to flash requires special protocols, but program download would normally only involve off-chip SRAM/SDRAM and on-chip RAM, and, possibly, general IO devices - all these can easily be written to.
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Could I only define a private interface/protocol to communicate with an Avalon MM master?
Could I use the the JTAG interface to download/programme NIOS II software program just like the nios2 command tools does? If using JTAG is possible, Could you point some related documentations out to me? Thanks.
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I don't think that Altera document the jtag debug interface, in any case it will need a lot more code on the host side.
Remember the jtag debug module isn't an avalon master, the nios executes code from within the jtag block to access the hardware registers of the jtag interface.
If you write your own avalon master, you have access to the memory (etc) independant of what the nios is doing - repeating hexdumps of memory are quite useful for working out what is going on (and without stopping the nios cpu itself).
You might actually be able to generate an 8 bit master - and have a bus width adapter generate the relevant byte enables. But some non-memory slaves may assume/require 32bit transfers.
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