How to constrain the JTAG in SOPC Builder

Hello everyone:

I have a DK-DSP-3C120N kit.Recently,I'm struggling with the DDR2 HP Controller under the direction of AN517(Using High-Performance DDR, DDR2, and DDR3 SDRAM With SOPC Builder).The design is targeted to the Cyclone® III EP3C120F780C7 Kit.

In this example,the SOPC system contain a Half-Rate DDR2 Controller working at 150MHz(altmemddr_auxfull),the PLL of the controller simultaneously generate a 75MHz output clock(altmemddr_sysclk) which been used as SOPC system clock.

After compilation,I got three critical warning,cause by JTAG.The TimeQuest report negative slack(-2.435) in Summary(Removal) of altera_reserved_tck.

The Top Failing Paths (Removal:altera_reserved_tck) is this:

Slack:-2.435

From---altera_reserved_tck

To-----pzdyqx:nabboc|pzdyqx_impl:zdyqx_impl_inst|FNUJ6967

I've tried to slow the DDR2 clock down to 133.333MHz,the NIOS clock down to 66.667MHz,but the slack value still negative.

I lose my head of this because I've constrained the JTAG using the templet:# JTAG Signal Constraints constrain the TCK port

create_clock -name tck -period 100.000 [get_ports altera_reserved_tck]# Cut all paths to and from tck

set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port

set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port

set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port

set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]

I didn't know what's wrong with it.

Can anybody help me?

Thank you very much!