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Benitez__Domingo's avatar
Benitez__Domingo
Icon for Occasional Contributor rankOccasional Contributor
12 months ago
Solved

How is Nios V's MHARTID csr register assigned a determined value?

Hello,

When multiple instances of the Nios V processor are integrated into a multiprocessor SoC, access to the MHARTID csr register when they execute concurrently is needed to identify the hardware thread.


The Parameters tab of the configuration screen for Nios V in the Platform Designer tool does not allow assigning any value to the MHARTID register.


For Nios II, there is a parameter for manually assigning the CPUID control register value, but for Nios V I do not see a similar parameter.


Then, my question is: how is Nios V's MHARTID csr register assigned a determined value?

Regards,

Domingo.

Nios Architecture
  • tehjingy_Altera's avatar
    tehjingy_Altera
    12 months ago

    Hi


    The Quartus 24.1 Standard is expected to be release by early March 2025.


    Regards

    Jingyang, Teh


7 Replies

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    12 months ago

    Hi


    I’m glad that your question has been addressed, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    12 months ago

    Hi


    The Quartus 24.1 Standard is expected to be release by early March 2025.


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    12 months ago

    Hi


    For the MhartID, it is only available starting from 24.1.

    For versions older than 24.1 it can not be set.


    Regards

    Jingyang, Teh


    • Benitez__Domingo's avatar
      Benitez__Domingo
      Icon for Occasional Contributor rankOccasional Contributor
      12 months ago

      Hi,

      Since I am trying to implement a Nios V/m multiprocessor on a Cyclone IV-based board and Quartus Prime Pro 24.1 cannot be used for Cyclone IV devices, I have to wait for the next Quartus Prime Standard version.

      When will a new Quartus Prime Standard version be available?

      Regards

      Domingo

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    12 months ago

    Hi

    For the MHARTID, this could be set in the platfrom designer under the NiosV IP parameters shown below:

    Regards

    Jingyang, Teh

    • Benitez__Domingo's avatar
      Benitez__Domingo
      Icon for Occasional Contributor rankOccasional Contributor
      12 months ago

      Hi,

      Thank you for your response.

      I am using "Platform Designer 23.1 Build 991 (Quartus Prime Version 23.1std.0 991 11/28/2023 SC Standard Edition)" and these are the options available:

      As you can see, there is no parameter for MHARTID.

      Which Quartus Prime and Platform Designer versions should I install to allow modifying the MHARTID csr register?

      Regards

      Domingo

      • Benitez__Domingo's avatar
        Benitez__Domingo
        Icon for Occasional Contributor rankOccasional Contributor
        12 months ago

        Hi,

        I would like to provide additional information. I need to use Quartus Prime Standard Edition because the FPGA device where I am configuring a Nios V/m processor is Cyclone IV. The latest version of Standard Edition for Windows is 23.1.1.

        As described in the Nios® V Embedded Processor Design Handbook (Updated for Intel® Quartus® Prime Design Suite: 23.4, date: 2023.12.04), Figure 10 at page 20, the parameter for Nios V/m Microcontroller Intel FPGA IP named "CPU Architecture" has a single option: Enable Pipelining in CPU. The parameter for the MHARTID csr register is not included.

        Then I think your previous answer is based on a Quartus Prime 24.x version.

        Is that right?

        Regards,

        Domingo.