How important are System Design Contraint (*.sdc) files?

Ted,

I was able to constrain my critical path, but like you said, I may have to change my design. I'm getting over 8ns slack on a 125Mhz clock (as seen in attached), but for some reason it will still work if I load the board a second time with the same *elf. Would this slack be overcome by either introducing additional clock sources (one per Ethernet interface) or using the "read latency" feature in Qsys component builder? I'm thinking the former would be a better.

At any rate, thank you greatly. I went through the overview at altera timequest demo video (https://www.altera.com/education/demonstrations/timequest/timequest-demo.html) to get me started. It seems timing was definitely my issue. For those experience the same learning curve, intel altera timequest timing analyzer resource center (https://www.altera.com/support/support-resources/design-examples/design-software/timequest/sof-qts-timequest.html) and the alterawiki timing constraints (http://www.alterawiki.com/wiki/timing_constraints) are great resources.