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Hi Alex,
Please refer to the Getting Started with Peripheral Register Visibility section of the SoC EDS User's Guide (
http://www.altera.com/literature/ug/ug_soc_eds.pdf). I think that should answer your question.
Regards,
Sue
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Hi Scozart,
Thank you for your reply!
But my question is that I cannot get data from fpga2hps bridge via Arm-Linux Application.
In my design, the following steps I used in my project:
1. The FPGA master have been implemented in FPGA2HPS bridge, I used the signals (user sideband signal, write address signal, write address valid signal, write data signal, write data valid signal )
2. In ARM side, I use the ACP ID Mapper Register. The dynrd and dynwr registers has been set the 5-bits user(according to user sideband signal) and 2-bits Page(I remap the 3rd 1GB memory).
3. I maped the address in Linux application , access to e.g. 0x80004000 (3rd page) address, but the data have not changed .
Did I miss some steps? Or misunderstand something?
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