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Altera_Forum
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14 years ago

How can I direct run nios programmer on epcs?

if i have not ram and less onchip mem,

How can I direct run nios programmer on epcs or sd card ?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You can't.

    The EPCS ROM and sd card devices can only be read by device drivers (etc).

    You could arrange to map multiple functions to the same addresses and load the code blocks are required (overlay loader) - but I'm not sure that has really been done since paged memory systems became common in the late 1970s.

    Another option is to enable the mmu, take the page faults and use that to dynamically page in the required code - but that is a lot of coding, and I suspect you won't have enough real memory for a reasonable set of working pages.
  • Altera_Forum's avatar
    Altera_Forum
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    thank you.

    can I use the serial RAM for example 23k256,because the FPGA pins is used full,do not use the parallel RAM.

    `timescale 1ns/10ps

    module M23K256 (SI, SO, SCK, CS_N, HOLD_N, RESET);

    input SI; // serial data input

    input SCK; // serial data clock

    input CS_N; // chip select - active low

    input HOLD_N; // interface suspend - active low

    input RESET; // model reset/power-on reset

    output SO; // serial data output

    // *******************************************************************************************************

    // ** DECLARATIONS **

    // *******************************************************************************************************

    reg [15:00] DataShifterI; // serial input data shifter

    reg [07:00] DataShifterO; // serial output data shifter

    reg [31:00] BitCounter; // serial input bit counter

    reg [07:00] InstRegister; // instruction register

    reg [15:00] AddrRegister; // address register

    wire InstructionREAD; // decoded instruction byte

    wire InstructionRDSR; // decoded instruction byte

    wire InstructionWRSR; // decoded instruction byte

    wire InstructionWRITE; // decoded instruction byte

    reg OpMode0; // operation mode

    reg OpMode1; // operation mode

    reg Hold_Enable_N; // hold enable - active low

    wire Hold; // hold function

    reg [07:00] MemoryBlock [0:32767]; // SRAM data memory array (32768x8)

    reg SO_DO; // serial output data - data

    wire SO_OE; // serial output data - output enable

    reg SO_Enable; // serial data output enable

    wire OutputEnable1; // timing accurate output enable

    wire OutputEnable2; // timing accurate output enable

    wire OutputEnable3; // timing accurate output enable

    integer tV; // timing parameter

    integer tHZ; // timing parameter

    integer tHV; // timing parameter

    integer tDIS; // timing parameter

    `define READ 8'b0000_0011 // Read instruction

    `define WRSR 8'b0000_0001 // Write Status Register instruction

    `define WRITE 8'b0000_0010 // Write instruction

    `define RDSR 8'b0000_0101 // Read Status Register instruction

    `define BYTEMODE 2'b00 // Byte operation mode

    `define PAGEMODE 2'b10 // Page operation mode

    `define SEQMODE 2'b01 // Sequential operation mode
  • Altera_Forum's avatar
    Altera_Forum
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    Years ago back in the nios forum days someone posted an EPCS controller that would allow you to do this. Mind you it would be incredibly slow and you don't want to use it for rwdata, heap, or stack otherwise you'll kill the Flash cells pretty quickly.

    If your board is still in development I would recommend slapping a x8 DDR SDRAM on it since even if you get a controller that will allow you to run code in place out of flash, or page in code it's going to be pretty slow.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks BadOmen ,Now only to modify my designed,but I 'm very interesting for run programm on epcs, other rwdata, heap, stack on onchip_mem,Can you tell me that post link?

  • Altera_Forum's avatar
    Altera_Forum
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    This was a long time ago (4+ years) so I'm not sure if that design is still around let alone if the post for it was salvaged when the nios forum went belly up (it was a forum user that created it and not Altera). That said what kind of performance are you looking for with such a solution? I ask because if you managed to run code out of an EPCS device the performance is going to be really bad and all this work isn't worth it if you have performance numbers to meet. If you need code performance then you'll need to page in code to on-chip RAM like DSL said, but this can be a lot of work as well.

    If you haven't already looked at code optimizations for reducing your footprint I recommend doing so over executing code out of the EPCS memory directly since that would make a world of difference in terms of execution speed. Running code out of EPCS with the appropriate controller would be like running an 8-bit CPU at 1MHz......
  • Altera_Forum's avatar
    Altera_Forum
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    Thank you very much,Where to select "over executing code out of the EPCS memory" ,I want to try,speed is not problem.