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Honored Contributor
14 years agothank you.
can I use the serial RAM for example 23k256,because the FPGA pins is used full,do not use the parallel RAM. `timescale 1ns/10ps module M23K256 (SI, SO, SCK, CS_N, HOLD_N, RESET); input SI; // serial data input input SCK; // serial data clock input CS_N; // chip select - active low input HOLD_N; // interface suspend - active low input RESET; // model reset/power-on reset output SO; // serial data output // ******************************************************************************************************* // ** DECLARATIONS ** // ******************************************************************************************************* reg [15:00] DataShifterI; // serial input data shifter reg [07:00] DataShifterO; // serial output data shifter reg [31:00] BitCounter; // serial input bit counter reg [07:00] InstRegister; // instruction register reg [15:00] AddrRegister; // address register wire InstructionREAD; // decoded instruction byte wire InstructionRDSR; // decoded instruction byte wire InstructionWRSR; // decoded instruction byte wire InstructionWRITE; // decoded instruction byte reg OpMode0; // operation mode reg OpMode1; // operation mode reg Hold_Enable_N; // hold enable - active low wire Hold; // hold function reg [07:00] MemoryBlock [0:32767]; // SRAM data memory array (32768x8) reg SO_DO; // serial output data - data wire SO_OE; // serial output data - output enable reg SO_Enable; // serial data output enable wire OutputEnable1; // timing accurate output enable wire OutputEnable2; // timing accurate output enable wire OutputEnable3; // timing accurate output enable integer tV; // timing parameter integer tHZ; // timing parameter integer tHV; // timing parameter integer tDIS; // timing parameter `define READ 8'b0000_0011 // Read instruction `define WRSR 8'b0000_0001 // Write Status Register instruction `define WRITE 8'b0000_0010 // Write instruction `define RDSR 8'b0000_0101 // Read Status Register instruction `define BYTEMODE 2'b00 // Byte operation mode `define PAGEMODE 2'b10 // Page operation mode `define SEQMODE 2'b01 // Sequential operation mode