--- Quote Start ---
True you can't use .sof files without the JTAG connection. You won't be able to use the nios downloader or nios programmer either to run your software.
What you will need to do is to compile your software, convert the .elf to a flash file and put it in the flash with the Quartus programmer. When converting to a flash file you will need to provide the fpga design so that the .elf file is mapped just after the FPGA image on the flash.
Ensure too that the CPU has his reset vector set to the EPCS controller so that it will load the software when it boots.
If you have two spare pins you can use them as a serial bus, with a UART core. This can ease debugging and communication with the CPU.
--- Quote End ---
Daixiwen,
I seem to have the same problem with the SBT Flash programmer - it requires that a jtag debug core be present in the device design. (Table 1-1 of the Nios II Flash Programmer User Guide.)
Recall that my jtag signals are not connected: (TDO,TRST both NC, TDI,TMS both Vcc, TCK GND)
The EPCS Controller core documentation says the the boot loader from the EPCS core copies the image to ram, then changes the program counter to transfer control to the program in RAM.
Can't I just bypass the loader and start executing code straight from an OnChip ROM?
I have spare pins and I/O. Adding a UART core is a great idea. Once I get the cpu to boot and execute my simple program to count out a PIO interface, UART willl definitely be one of the first things I add. (I love printf debug!)
Honored Contributor
