If you can't load the fpga over JTAG, I doubt the JTAG debug will work either.
If you remove the JTAG debug module you might find that the nios cpu actually comes out of reset - it will exectute the EPCS boot code.
Might be worth arranging to put some simple code (eg LED flashing) in some other internal memory at the reset address to prove you can get the nios running before attempting the EPCS code bootstrap.
If you have anything you can use to act as an avalon master it will make software debug somewhat easier! We used an 8-bit PIO slave with a few address bits writing each 32bit address/data as 4 8-bit values, you could use a serial port 4bits command + 4bits data to have the same effect!