Honored Contributor
Honored ContributorUsing a .sof is easier during development because you don't have to program the flash.
Do you have a usb blaster connected in JTAG mode with the FPGA? Is the FPGA detected correctly by the Quartus programmer? Did you enable the JTAG debug module in the Nios CPU? ------- Here's some background - this board has been used for something else, but we are considering using it for a different application. This would be our first Nios based design. The application that currently uses the board was developed in Quartus and can be programmed to the Serial Config device using the pof file and a USB Blaster. I did a bit of digging yesterday and found a document on the altera web: ../literature/hb/agx/agx_52011.pdf See pages 42 and 84 for the difference between configuration using a serial device (in this case EPCS64) and JTAG. After finding that, I dug out the board schematic and found the following: MSEL[3..0] = 1000 (as expect from the Figure 11-15 p.42 in the pdf) nSTATUS, nCE, DCLK, CONF_DONE, nCEO, nCONFIG, nCSO, DATA0 and ASDO are also wired as expected. -> no surprise here. As I mentioned, the part can be programmed using the USB blaster in Active Serial Mode. However, when I compare my PCB schematic with Figure 11-35 (p.84) I find the following: TDO - no connect on my PCB. TDI - pullup to VCC on my PCB TMS - pullup to VCC on my PCB TCK - pulldown to GND on my PCB TRST - no connect. All of this leads me to the conclusion that I cannot use the jtag uart for debug. I'm not even certain that I can use an sof file with this board configuration. Thoughts? ----------------- I'd still like to use this board for a nios based project.
