Help: about the socp setting

Hi,

Thanks BadOmen and larsen. But I still have questions.

I want to run the firmware in on_chip_ram. The reset address should be the EPCS4 address. The flash loader program copys the firmware from epcs4 and relocates it to the on_chip_ram. The exception address should in the on_chip_ram address. So maybe the exception handlier will conflit with the firmware. For example, the EPCS4 start address is 0x000000, the on_chip_ram start address is 0x1000000, so the reset address is setted at 0x000000, and the exception address is at 0x100020, is it OK? Why?

I can controll the external RAM or FIFO using Avalon registered bus. How can I create the HAL drivers for on_chip_ram, FIFOs, or user logic? If I use the full flag to interrupt the niosII, how to do?

I have read some Altera documents but finf no answers. What documents shopuld I read?

Thanks!

eRen