harware development board layout

hi

thanks for you replies.

i knew than i should do the schematic myself, the problem was for footprint, it can be a very stupid mistake if the card don't work because we done a wrong footprint!!!! but it's allright, i done it, and i will chech and chech again...

we will use external, SDRAM, EPCS and FLASH to run a nios program. we will use I2C protocol for communication (from opencore.org IP, we are currently testing it on a 1c12 devellopment board). we would like to use ethernet but the ethernet MAC/PHYS controller take too many pins so i think we will have to forget it. we will use a multilayered PCB (it should be very hard to make a double layed ). we will use the sames components than in Altera's development boards, for not have to do the nios IP's.

i hearn than the Flash S29GL064M11TAIR00 can be use in place of the AM29LV065DV-120REI, is it true and does someone tested it?

we should use an MT48LC4M32B2 RAM because it is a 32 bits RAM so we just have to put one in the card (we are trying to make the smallest card as possible)

we use the schematics of development board for helping us to understand exactly how everytings works and to prevent mystake but we have a problem with Altera's shematics because they use CPLD. so we can't see exacly what is done. does someone have a shematics where a Cyclone is use for nios II aplication where we can look for the connections between FPGA and Flash, RAM... ? i will be very pleased if someone may send me one at nedelec.ronan@caramail.com

by reading the Altera's datasheets i think it's OK but may someone confirm than we can use the Flash programmer on a custom board without CPLD (i have a problem with RY/BY of the Flash, it haven't any connection with nios and i don't know where place this pin).

thanks

ronan