[Hardware Testing]How to connect the jtag-MM in Top level. ref. [Low Latency Ethernet 10G MAC Intel Cyclone 10 GX FPGA IP Design Example User Guide]

Hi Asey,

I presume you are referring to Cyclone 10 GX 10G Ethernet example design from below link

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20162.pdf

If you are using Cyclone 10 dev kit board

• Then make sure you configure the on board clock generator frequency correctly as per attached pic
• JTAG master rely on on-board JTAG connection. You want to check to ensure your JTAG connection is working as well. You can use "jtagconfig" command to verify on board JTAG connection or run "jtagconfig --setparam 1 JtagClock 6M" command to reduce JTAG frequency to improve the signal quality
• You are running Avalon-ST loopback via "source loopback_conf.tcl". This is the loopback where external Ethernet tester generate traffic to FPGA Eth RX pin, loopback internally inside FPGA and then re-transmit back to FPGA Eth tx pin then to Ethernet tester. So, you need to verify your tester setting as well

else if you are using your own board

• Then make sure you configure all the FPGA pin assignment correctly and double check your board FPGA power, JTAG, clock and reset connection before you run the Ethernet testing

Thanks.

Regards,

dlim