Hardware interrupts from FPGA to HPS

maybe can do something like this?

https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/fpga_faqs

Thank you for quick response.

I'm able to see interrupts like spi, eth, uart, etc(cat /proc/interrupts in Yocto). But I don't know how to get GPIO interrupts (from what I've understood located from 72 to 135).

After the qsys and Quartus compilation what steps I have to do to make GPIO interrupts work?

Should I create/edit device tree and how? How should I create uboot file(using bsp tool or I must use bitbake command to generate it)? Should I create new preloader or I can use preloader which is provided with Altera examples? Should i download Yocto source and compile it with bitbake and load the compiled kernel to sdCard?(could this be avoided?) should I write a driver for linux to be able to see the interrupt and should I compile it the new linux kernel?

I know it's a lot of questions but after trying most of those things and reading forms and youtube videos, I'm confused...

Until now I didn't find any good explanation what should be don't to create hardware interrupt.

I would be very glad to get some help.

Thanks in advance

Boris

Hi, I the GPIO interrupt setting with hps need to be done by software register configuration, it is mainly in the application layer of the arm already.

if we go for bare metal usage to have clearer usage of the interrupt. some example for bare metal type.

https://www.altera.com/support/support-resources/design-examples.html#soc-design-examples

Hi,

I'm trying to configure the interrupt controller using Altera tutorial :ftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/using_gic.pdf

However, when I run the code example provided in the tutorial I'm getting Segmentation Fault in command: *(int *)address |= value;

and the address is: address = 0xFFFED100 + reg_offset;

I understood that the base address of the interrupt controller is 0xFFFED100.

Do you know what may be the problem?

Thanks,

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Hi,

I have data bus that I want to send to a PC each time we get an interrupt from FPGA module (maximum interrupt frequency is 1MHZ and the throughput should be 8 Mbytes/sec) through Ethernet.

I have a problem with implementing an interrupt to ARM(Cortex A9) processor from FPGA.

I'm using DE1-SOC development board which contains Altera's Cyclone V device. This device is combination of FPGA and ARM.

I'm running Linux Yocto on the ARM processor and I have a problem with making the Linux OS recognize an interrupt from FPGA module.

Basically I want the embedded Linux OS recognize a new hardware interrupt.

The problem is that I don't see the hardware interrupt in Linux by running "cat

/proc/interrupts" command.

After I compile Quartus (and configured the PIO to be an interrupt from FPGA to HPS in Qsys) what should I do in order to make the interrupt in Linux OS?

Can anyone help me please?

If there is another way (or better way) to perform the data transfer I would be glad to know.

Thanks in advance

Boris

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Hi Boris,

I'm trying to use the ethernet communication on the DE1-SoC board. But I didn't found any example in C for the HPS side and in VHDL or Verilog to the FPGA side. Could you help me?

Regards

Gianluca