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Honored Contributor
Honored ContributorHard Processor System's AXI SDRAM
I'm trying to create Qsys project that connects a simple AXI peripheral in the FPGA to the hard processor system for the DE0-Nano-SOC dev board/Cyclone V. However, the Arria V/Cyclone V HPS IP contai...
Altera_ForumHonored Contributor
Honored Contributor1) these interfaces are to connect SDRAM to FPGA fabric: export data & clk signals to FPGA or connect in Qsys with another IPs.
2) If you desactivate these interfaces in Edit menu of HPS, then the FPGA can't read/write SDRAM directly
