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Altera_Forum's avatar
Altera_Forum
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8 years ago

Hard Processor System's AXI SDRAM

I'm trying to create Qsys project that connects a simple AXI peripheral in the FPGA to the hard processor system for the DE0-Nano-SOC dev board/Cyclone V. However, the Arria V/Cyclone V HPS IP contai...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

1) these interfaces are to connect SDRAM to FPGA fabric: export data & clk signals to FPGA or connect in Qsys with another IPs.

2) If you desactivate these interfaces in Edit menu of HPS, then the FPGA can't read/write SDRAM directly