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Honored Contributor
Honored ContributorH2F Bridge EMIF Access
Hi, I am using an Arria 10 ReFLEX Achilles dev kit that includes 2 DDR4 memories. The first DDR4 is used by the HPS and the second one I am trying to access from the HPS as well. To do this, I am ...
Altera_ForumHonored Contributor
Honored ContributorHi VijeyShankar,
My data bus for my DDR4 is 32 bit and my HPS output is also 32 bit. I have no problems accessing the DDR4 now. What ended up being the problem with my project is there was a timing problem and my timing requirements for the DDR4 was not met. I fixed that by adding some pipelineing between the multiple masters I have accessig the DDR4. I wrote the data from the HPS by using /dev/mem and mmap to read and write data to the DDR4 using the hps2fpga bridge.
