Hi Arthur,
Yes and no...
The HPS_LTC_GPIO point is not actually connected to a pin on the LTC connector. The schematic shows a "DNI" next to R105 that I missed initially. I found no other GPIO points to use on the connector. So then my focus shifted to using HPS_I2C1_SDAT and HPS_I2C1_SCLK (which can be used as GPIO) and I was able to do this, but it took a number of steps:
* you have to open a suitable Quartus job (I used ...\DE0-Nano-SoC_v.1.1.0_SystemCD\Demonstrations\SoC_FPGA from the DE0 CD) , open Qsys within it, and in the "Parameters Panel" of the hps_0 component find the "Peripheral Pins" tab.
* de-select the I2C1 peripheral and then scroll down and "push" (select) the GPIO "buttons" for GPIO 51 and 52.
* generate the HDL, return to Quartus.
* Edit the top level port file (e.g. ghrd.v) - you need to remove the lines:
// .hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C1_SDAT ), // .hps_io_i2c1_inst_SDA
// .hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C1_SCLK ), // .hps_io_i2c1_inst_SCL
* Add instead something like:
.hps_0_hps_io_hps_io_gpio_inst_GPIO51 ( HPS_LTC_GPIO_SDAT ), // .hps_io_gpio_inst_GPIO51
.hps_0_hps_io_hps_io_gpio_inst_GPIO52 ( HPS_LTC_GPIO_SCLK ), // .hps_io_gpio_inst_GPIO52
* Also remove:
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
* Add instead:
inout HPS_LTC_GPIO_SDAT,
inout HPS_LTC_GPIO_SCLK,
* Assign voltages for these new pins with the "Pin Planner" under the "Assignments" menu. Find/add the signal names (HPS_LTC_GPIO_SDAT/SCLK) and select 3.3V LVTTL.
* Build the Quartus project.
* When finished, grab the output from the hardware handoff folder (hps_isw_handoff) and use that to build a new u-boot SPL using the Altera EDS tools - I initially followed this process to generate the SPL -
https://rocketboards.org/foswiki/view/documentation/gsrd131preloader.
* But generating just the SPL didn't work so I then used the latest u-boot v2016.03 from the u-boot git repo to generate both SPL and u-boot image.
* To do this I used
qts-filter.sh found in the u-boot source at .../u-boot/arch/arm/mach-socfpga.
* Applied
qts-filter.sh to the output of the BSP Editor run during my first attempt to generate the SPL.
* Dropped the resulting files from
qts-filter.sh back into the u-boot source (overwriting the ones that were there) at .../u-boot/board/altera/cyclone5-socdk/qts
* Then I rebuilt u-boot from the top level directory in a crosstools-sourced environment with make socfpga_de0_nano_soc_defconfig , make all
* And.. copied the resulting u-boot-with-spl.sfp product to the 'A2/unknown' partition of the MMC.
Of course, if you are unlucky like me, then you have a board that fails memory calibration with the latest u-boot build. It looks something like this:
U-Boot SPL 2016.03 (Mar 28 2016 - 16:34:29)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
drivers/ddr/altera/sequencer.c: Calibration complete
SDRAM calibration failed.
# ## ERROR# ## Please RESET the board# ##
The u-boot maintainers are looking into this.... In the meantime, I bought a second DE0 board and that one works. (I have two boards that don't, failing memory calibration).
Lastly, disable the I2C1 component from the device tree of the Linux kernel you will boot on the MMC. Once in Linux you will see that you have control over those two GPIO pins.
I was able to control output state via the user space GPIO interface after adding a 10k pull-up resistor to the LTC pins connected to these GPIO points.
Simple as that ;)
Good luck!
--George Broz
Moog Industrial Group
Honored Contributor
