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Altera_Forum
Honored Contributor
9 years agoFor what it's worth, I just finished debugging an I2C interface that had very similar issues and found this knowledge base item from Altera was the cause. I did some digging in the Chip Planner (Arria 10 w/ Q16.0) and found that my tristate buffer in SDA and SCL was always driving (!OE = GND) and control signal was wired to the BUF_IN port. This is exactly the opposite of what I was expecting (!OE = control and BUF_IN = GND). Therefore, we were always driving the bus and the half-voltage on the SDA pin was a function of the two ends fighting each other.
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01262015_264.html The solution is to create a psuedo-ground signal and set an attribute to keep it in the synthesizer. Confirmed that this fix resulted in a working I2C bus and the Chip Planner also confirmed that they were utilized properly in the IO buffer.