Honored Contributor
Honored ContributorHi,
--- Quote Start --- Indeed, the 'hardware' SCL and SDA pins are open-drained with a 4k7 resistor, so I configured them as such in the module I wrote. Our design uses the basic altera GPIO, and I came upon this webpage: http://www.alterawiki.com/wiki/gpio where the author uses the opencore GPIO instead of the basic altera GPIO. So, do you think the bug I cope with can come from this difference? --- Quote End --- At first, please check the resistor's value, soldering of SDA line, m41t83's power line. And check the rising and falling time of SCL. It must be < 300ns. Please refer http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/cd00127116.pdf at pp.53. If the rising time of SLC is not enough, it is one method to set the SLC hardware pin as output. In the i2c-gpio method, SCL and SDA signals are generated directly by your Nios CPU, and this is the reason why the SLC clock period is not constant. If you have any doubt, there is another way to use an 'opencore's i2c core'. Kazu
