Generating BSP failed: Cpu reset memory has no matching memory region.

Update (this is what I think is behind my problem):

- After analyzing with an XML viewer the SOPC file, I see that the catalog components that expose a Avalon instruction master interface of type 'S1' all end up with a linker memory region in the BSP editor. Those that do not (JTAG / debug mem / sram ...) do not get a linker memory region. XML: "nios2_gen2.instruction_master/sdram.s1" <endConnectionPoint> = S1

- Since my SRAM component does not expose an S1 interface, I assume it cannot be used correctly as Avalon instruction master.

- I tried to add a memory device manually (BSP add memory device) and linker memory regions (reset region + sram region) and succeeded in mapping the .bss, .entry, .heap, .rodata, .stack and .text to the SRAM chip manually. However, this was of no use because the BSP editor would not generate an application with these settings because they did not correspond to the data in the .sopc. (reset and exception vector regions not ok). For the last problem I did not find a solution.

- There are some references that explain that you need to set the isMemoryDevice = 1. This is done for the sram block by checking the "use as pixel buffer for video out" checkbox in the sram parameter settings in Qsys. However, this did not solve the problem. (found this by analyzing the Sram tcl file).

Best Regards,

Johi