Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Generating BSP failed: Cpu reset memory has no matching memory region.

Hello Everybody, I have a Nios II /f that runs "Hello world" properly on a DE2-115 in Q16.0 using FPGA on chip memory. The system is as simple as possible, cpu, jtag, ram, sysid, it runs at...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hello TCWORLD,

Thank you for the clarification of my rather cryptic statement.

However i am a bit stuck in the same area: Removing my FPGA based RAM and inserting Sram in its place in another test application i am working on i get:

INFO: Tcl message: "No system timer device"

WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "nios2_gen2_0" has no memories connected to its Avalon master(s)

SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"

SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"

In this case i cannot modify the BSP because no project is generated in Eclipse.

Can you give me a direction what to do in this case ?

Am I doing something completely illegal with my configuration where there is only a DE2-115 SRAM and a CPU? Maybe I need to add some onchip ram so the sram controller can get initialized properly, but my knowledge does not go far enough for to know this. What makes me think in this direction is that the SRAM has no .s1 extension when i select it in the cpu reset vector box. The SDRAM and FPGA RAM do have this extension.

Many thanks,

Johi.