FPGA-to-HPS SDRAM Bridge in Bare-metal

Hello all,

I have the same problem but unfortunaly I am not as experienced on SOC system to resolve the issue.

I'm trying to port a design from a Cyclone 5 (not SOC) to a Cyclone 5 SOC.

I'm using a DE1-SOC from Terasic (seems to be a commun dev kit).

My first step is to keep every thing like it is but just changing the DDR3 memory controller to use the HPS one.

So in my qsys system I instanciate the HPS with only the FPGA-to-HPS SDRAM Interface with Avalon-MM and 64 bit width.

All the other AXI bridges are set to Unused.

For the configuration of the DDR3/SDRAM timing I copy from a kit design example.

Then I try to follow the http://www.alterauserforums.org/forum/showthread.php?t=47099 bare metal example since I only want that the DDR3 be set, FPGA-HPS SDRAM interface be configured.

Of course it doesn't work (plus now I have the "Target Message: Could not determine target state" message but that is another problem, I think first I need to know better the design flow)

But I am a bit lost. I don't know if I need to generate the BSP ? I don't have a SD card so no Linux or other complex system.

The only thing I know is that I have to make the preloader working since it is on that stage that the HPS configure the pins et interface.

This is the first time I use a HPS, before I used to use the simple nios 2 ^.^.

A lot of design reference use a SD card with Linux....which is too complex system for my application.

The constraint is that I don't want to erase the default bitstream saved in the EPCQ on the developement kit.

If it is possible to have every working on the "temporary memory" will be great. like programming the .sof with signal tap then using eclipse to program the HPS (Like what I used to do with the nios2)

I'm on a debuging process so, don't want at all to save in flash, epcq and to break something that will be difficult to recover....

I will be glad if someone can guide me and show me the way to go.

Thanks in advance.