FPGA-to-HPS SDRAM Bridge in Bare-metal

FYI I recommend using the modular SGDMA cores instead of the read and write master templates. The mSGDMA gives a superset of features and it's a standard IP shipped in Qsys. If you want to control the mastering logic with your own logic simply instantiate the read or write master by itself and connect your logic up to the command and response ports. For more information see the documentation here: http://www.alterawiki.com/wiki/modular_sgdma