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Altera_Forum
Honored Contributor
Honored ContributorFPGA-to-HPS SDRAM Bridge in Bare-metal
FPGA-to-HPS SDRAM Bridge in Bare-metal I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V. I'm trying to read data from SD...
Altera_ForumHonored Contributor
Honored ContributorHi,
This may be what you need. I found it on Altera website... Please see the attachment. ---------------------------------------------- Custom read and write master templates ---------------------------------------------- This design requires the Quartus II design software 8.0 or later. Each template allows you to easily access the system interconnect fabric using a simple start and acknowledge protocol to control the data movement. To learn more refer to the file "Avalon_MM_Masters_Readme.pdf" available from with the file "exm_avalon_mm_master_templates.zip". .
