FPGA memory initialization and management

The address changes depending on where you are in the design.

1. On an altsyncram component, with 32-bit data width, incrementing the address +1 increments the data by a 32-bit word.

2. Qsys slave addressing is word-based. So, on a Qsys Avalon-MM slave interface, with 32-bit data width, incrementing the address +1 increments the data by a 32-bit word.

3. Qsys master addressing is byte-based. So, for a master accessing an Avalon-MM slave interface, with 32-bit data width, incrementing the master address +4 increments the data by a 32-bit word.

The Altera hex editor works fine. I typically create a couple of words in an example file using the hex editor, save it as Intel hex format, and the look at that file relative to the Intel hex standard. For 32-bit words, I'm pretty sure the Intel hex format will be one 32-bit value per line in the file. I then write code (C, MATLAB, or Tcl) to create the hex file.

Cheers,

Dave