Altera_Forum
Honored Contributor
8 years agoFPGA Bridge enabled, but signal tap shows data is zeros
Thanks in Advanced.
Previously I have done the same thing on a Macnica Sodia board but used the FPGA DDR memory to do the same thing -- so I HAVE VERIFIED that my firmware works as advertised. Currently - I want to use HPS DDR to reduce the DDR chips needed for our custom PCB so ... I am working on a Macnica Helio board took the Q14.1 Golden Design and added my IPs then - I have used Q17.1 bsp-editor and associated commands to generate the u-boot and preloader. If necessary I can provide those instructions. I am using kernel 4.1.33-ltsi with some extra features enabled. At first my *.dtb file was not correctly resetting the bridge, but subsequently I changed the *.dtb (and from another post I matched it to the *.dtb of the kernel). AND I can see during boot [ 2.272449] fpga_manager fpga0: Altera SOCFPGA FPGA Manager registered [ 2.279599] altera_hps2fpga_bridge sopc@0:fpgabridge@0: fpga bridge [hps2fpga] registered [ 2.288011] altera_hps2fpga_bridge sopc@0:fpgabridge@1: fpga bridge [lwhps2fpga] registered [ 2.296481] altera_hps2fpga_bridge sopc@0:fpgabridge@2: fpga bridge [fpga2hps] registered And I can see everything in /sys/class/fpga-bridge/ I HAVE SIGNAL TAP SET UP TO SEE THE avs and avm signals --> I have a device driver that has a kernel buffer of known data and I give the firmware that start address to read from BUT I can see all the correct bus signals but the data read from the address IS NOT THE EXPECTED DATA IT IS ZERO !!! What am I missing? IS MY KERNEL NOT IN SYNC?? Also, how do I know the address of fpgabridge@0, @1, @2 - to verify that they match properly (it used to be at boot you saw the actual addresses). Any help/ideas will be greatly appreciated !!!