Honored Contributor
Honored Contributor
i'd still like to hear other developers views about how strictly we need to keep within fmax. i know it amounts to 'over-clocking' and should be avoided but if i get to within 1% of fmax it could save me maybe two days of re-compiling.
i've never issued a build to a customer that didn't meet fmax but i am now developing s/w on a board that only achieved 64.1mhz (target 65mhz). i'll play with it for a week or so and let you all know if i get any odd happenings.
i should have mentioned earlier that i'm stuck with my particular cyclone part, ep1c12 as parts with more logic cells have a different footprint. also i'm using speed grade 7.
thanks all.
banx.
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--- Quote End --- Quartus reports Fmax based upon statistical data. It is worst case for that die at worst case temperature. When the parts are produced they are binned for the speed grade. You are not in the fastest speed grade part. A potential solution for you would be to go to the -6 speed grade part, but it will be more expensive. As the process yields improve they will sell -6 speed grade parts as -7s because the part is guaranteed to run faster. You can try to improve your Fmax by changing the seed number. But DSE will give you the best results, by telling you what synthesis options will give you best results. The most appropriate fix for your design is to find out what paths are having trouble meeting timing and fixing those paths. There are a lot of ways to correct for not meeting timing (reregistering, multi-cycle, etc.). Your reference to overclocking isn't accurate. Do not ship parts that don't meet timing. The parts may not work when they get hot and/or a certain lot of parts produced will not work or behave erraticaly. I have heard however that there is some statistical confidence if you are within say 1% of Fmax. Perhaps an Altera FAE can help you further.
