Thanks Hippo. Some good pointers, I'll certainly investigate the space explorer.
I'd still like to hear other developers views about how strictly we need to keep within Fmax. I know it amounts to 'over-clocking' and should be avoided but if I get to within 1% of Fmax it could save me maybe two days of re-compiling.
I've never issued a build to a customer that didn't meet Fmax but I am now developing s/w on a board that only achieved 64.1MHz (target 65MHz). I'll play with it for a week or so and let you all know if I get any odd happenings.
I should have mentioned earlier that I'm stuck with my particular Cyclone part, EP1C12 as parts with more logic cells have a different footprint. Also I'm using speed grade 7.
Thanks All.
Banx.