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Altera_Forum's avatar
Altera_Forum
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14 years ago

Flip-flop by using logic gates

hi I am a new to VHDL and currently doing VHDL assignment. In this assignment, required to create the D, JK flip-flop. I need help to solve my error for my code as shown as below: l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

process(clk)
  begin
    if rising_edge(clk)then 
      Qi <=(J and (not Qi)) or ((not K) and Qi);
    end if;
    qn <=not Qi ;
    Q <= Qi ;
  end process;