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Altera_Forum
Honored Contributor
Honored ContributorFlip-flop by using logic gates
hi I am a new to VHDL and currently doing VHDL assignment. In this assignment, required to create the D, JK flip-flop. I need help to solve my error for my code as shown as below: l...
Altera_ForumHonored Contributor
Honored ContributorHi FvM
- use an internal signal Qi and copy it to Q outside the edge sensitive condition? can show me pls?
