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Altera_Forum's avatar
Altera_Forum
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14 years ago

Flip-flop by using logic gates

hi I am a new to VHDL and currently doing VHDL assignment. In this assignment, required to create the D, JK flip-flop. I need help to solve my error for my code as shown as below: l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Two options:

- change Q from out to buffer

- use an internal signal Qi and copy it to Q outside the edge sensitive condition.

Also the assignment for qn must be placed outside the rising_edge() condition, otherwise it's delayed by one clock.