Hi Ken,
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I haven't tested my SOPC components using the Avalon Verification IP Suite. I had assumed they were OK since the system worked 100% in Debug/Run mode but not with EPCS boot. Is this not the case?
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By not testing the components, you can never know if your components work 100% of the time.
Consider the case of a back-to-back read, or write, read followed by write, or write followed by read. These sequences are easier to generate with the verification IP suite than they are with a NIOS II processor, or DMA controller.
Lets say your component does have a problem with a write followed by a read, and that transaction sequence gets generated rarely. How would you determine that the reason for your system lockup was that particular problem?
I'd recommend simulating any Avalon components you create.
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I just found the solution to my problem on the forum, see link below;
http://www.alteraforum.com/forum/showthread.php?t=24156 My problem related to the JTAG UART SOPC component used by the Debugger and as suggested by RichardA, setting Stdin, Stdout and Stderr all to 'none', in the BSP editor, allowed the processor to run at power up. I can only assume that the JTAG UART's IRQ (0) was hanging my code and preventing system operation.
Thanks for your suggestion and offer, much appreciated.
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Glad to hear your current problem was resolved. Watch out for the next one though, it might be a little harder to fix :)
Cheers,
Dave