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Altera_Forum
Honored Contributor
15 years agoFlash Access Problems
We have a 3 processor design that all boot successfully from a single CFI flash (all reset addresses are set to our CFI Flash at different addresses). The firmwares run in different On Board Memories...
Altera_Forum
Honored Contributor
15 years agogoogle :-) (dekker mutex)
I've not looked at the sopc mutex component either, I've seen code snippets on here that might be trying to use it - but the interface seemed gross (via open() etc). I can imagine implemeting mutex in a logic block with multiple Avalon slaves (one for each master) where a write of '1' would stall writes on the other slaves (ie from the other masters) until a write of '0'.