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Altera_Forum
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15 years ago

Flash Access Problems

We have a 3 processor design that all boot successfully from a single CFI flash (all reset addresses are set to our CFI Flash at different addresses). The firmwares run in different On Board Memories...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The SOPC builder (etc) arbitrates each individual bus cycle.

This is ok if all you are doing is reads.

If you start doing writes and erases you need to ensure that no other accesses happen during the entire write/erase procedure. A sector erase is likely to take a significant fraction of a second.