FIFOED_AVALON_UART

I know the serial port issue has been covered again and again but I have a quick question on the FIFOED_AVALON_UART.

I'm trying to use the uart with an adjustable baudrate. It appears that the input clock to this is always the base clock and not the input clock that I define in SOPC Builder. Is this correct or is there a problem?

I'm trying to use the uart on a EP2C35 (Cyclone II dev board). This board has a base clock frequency of 50MHz. My system clock is actually 85MHz generated with a PLL. I have the input clock defined correctly (I think) in SOPC Builder but the divisor values I need for different frequencies are always based on the 50MHz clock.

Is this the way the component is designed or is there a problem with it?

Thanks