New ContributorFailed to boot NIOS II app from S25FL128SAGNFM001 using Intel GSFI
Hello,
I am having troubles with booting up a Cyclone V NIOS II app from S25FL128SAGNFM001 using Intel GSFI. I am using 22.1 tools.
I tried to follow the https://community.intel.com/cipcp26785/attachments/cipcp26785/fpga-wiki/926/1/Generic_Serial_Flash_Interface_design_example_quick_start_guide_final_updated.pdf
but have no luck. Sorry for a very long post.
Here is the Platform Designer NIOS setup
Here is the Intel GSFI /Flash setup
The NIOS application runs from the RAM and accesses the flash with no problems (for some reason my app reports Control Register = 0x82 instead of 0x101) but I cannot boot it from the flash.
Here are the BSP settings
Here is the mem_init_generate output (only serial_flash_top_0.hex is used)
17:02:22 **** Build of configuration Nios II for project app ****
wsl make mem_init_generate
Info: Building /mnt/c/Work/Projects/app/Cyclone_V/app_bsp/
make --no-print-directory -C /mnt/c/Work/Projects/app/Cyclone_V/app_bsp/
[BSP build complete]
Post-processing to create mem_init/boot_rom.hex...
elf2hex.exe app.elf 0x00018000 0x0001afff --width=32 --little-endian-mem --create-lanes=0 mem_init/boot_rom.hex
Post-processing to create mem_init/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.hex...
elf2hex.exe app.elf 0x00010000 0x00014fff --width=32 --little-endian-mem --create-lanes=0 mem_init/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.hex
Post-processing to create mem_init/serial_flash_top_0.hex...
alt-file-convert.exe -I elf32-littlenios2 -O hex --input=app.elf --output=mem_init/serial_flash_top_0.hex --base=0x03000000 --end=0x03ffffff --reset=0x03800000 --out-data-width=8 --boot="C:\intelfpga_lite\22.1std\nios2eds\components\altera_nios2\boot_loader_cfi.srec"
Converting Nios II ELF file to HEX file. Appending boot file.
Post-processing to create mem_init/hdl_sim/async_512Kx32.dat...
elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/async_512Kx32.dat \
--base=0x00400000 --end=0x005fffff --width=32 \
--little-endian-mem --create-lanes=0
Post-processing to create mem_init/hdl_sim/boot_rom.dat...
elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/boot_rom.dat \
--base=0x00018000 --end=0x0001afff --width=32 \
--little-endian-mem --create-lanes=0
Post-processing to create mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.dat...
elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.dat \
--base=0x00010000 --end=0x00014fff --width=32 \
--little-endian-mem --create-lanes=0
Post-processing to create mem_init/hdl_sim/ssram_0.dat...
elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/ssram_0.dat \
--base=0x00600000 --end=0x006fffff --width=32 \
--little-endian-mem --create-lanes=1
Post-processing to create mem_init/hdl_sim/async_512Kx32.sym...
nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/async_512Kx32.sym
Post-processing to create mem_init/hdl_sim/boot_rom.sym...
nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/boot_rom.sym
Post-processing to create mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.sym...
nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.sym
Post-processing to create mem_init/hdl_sim/ssram_0.sym...
nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/ssram_0.sym
I combine FPGA sof file and NIOS hex file into common jic file.
Any help will be greatly appreciated.
Thanks!
