Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi!
The solution for me was to re-compile UBOOT with the new hps.xml file generated by quartus. In this file, according to my design, the F2SDRAM port is enable, so the device at power up start with the good configuration. UBOOT factory configuration that I was using on the Achille development kit, only enable the HPS to FPGA LW bridge. Regards