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Altera_Forum
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7 years ago

F2H Avalon Bridge f2h_sdram0_data_waitrequest got stuck

Hi all, I met a problem hope someone can help. I am using f2h_sdram0 to access the SDRAM. After building HPS system, I got the hps.xml file in handoff folder, part of the code is: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi guys,

I'm facing the same problem with a slightly different design.

I have a Cyclone V SX with fpga2sdram enabled. Firmware is loaded by linux in userland with the device tree overlay method.

My DMA accesses are fine but once in a while, the wait_request signal get stuck at '1' and I have to reset the board to get it back to a functional state.

I have seen that there are several threads here with no answer from Altera. Also I found this article : https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/important_note_about_fpgahps_sdram_bridge;

I'll be glad to know if the problem is on the die and/or if there are some tips/workaround to make it work.

Cheers