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Honored Contributor
Honored ContributorExternal SSRAM reading/writing problem
Hello everyone, I want to connect nios core (cyclone ii) to external sram memory (cy7c1380d) but I'm experiencing a problem while reading/writing to/from the memory. For 2MB (data width 32 bit...
Altera_ForumHonored Contributor
Honored ContributorTo avoid misunderstanding , please clarify your exact address lines connection, nikola.
What dsl says about address ordering is correct. But I understood sram_a6 and ssram_a7 are driven by A19 A20, while A6,A7 from tristate bus don't drive anything, and this would lead to the situation I described. But probably your connection is like dsl thought: sram_a2 - A2 sram_a3 - A3 sram_a4 - A4 sram_a5 - A5 sram_a8 - A6 sram_a9 - A7 sram_a10 - A8 .... Is this correct?
