External bus interface

If you use the default list it gives you and connect the ones you need you should be fine. Even if you come up with a good name for each signal, it's going to tack some extra stuff onto that anyway. The default list will give you port names like: nios_processor_read_n where nios_processor was the name of the core.

Leaving extra ports (like read_n) disconnected is fine, but you should have those assigned to meet the avolon bus spec (it's a standard bus so you need to follow some form of a conviention). Any logic that feeds nothing gets synthesized out so don't worry about using up more LEs adding the whole port list and not using all of it.