external 16Bit Slave, shared signals

Hi Fischer,

The signals that pop out into an SOPCB system can be decoded as follows (I am borrowing your list of signals):

be_n_to_the sram_0 ???
chipselect_n_to_the_HFCE1_0 
ext_ram_bus_address 
ext_ram_bus_byteenablen ??
ext_ram_bus_data
ext_ram_bus_readn
ext_ram_bus_writen
read_n_to_the_sram_0
reset_to_the_HFCE1_0
select_n_to_the_ext_flash
select_n_to_the_sram_0
write_n_to_the_ext_flash
write_n_to_the_sram_0

- Anything with "ext_ram_bus" in it is a shared signal for all interfaces on the tri-state bus. This is because ext_ram_bus is the name of your tri-state bridge.

- You need not hook up every signal that is shared (ext_ram_bus) to every pin on every chip; some will not be required (for example, if you're talking to a chip with read/write_n input, or no byte enables). This is device dependant.

- The remaining signals are not shared - they should have the name of a peripheral in the SOPCB system. For example, write_n_to_the_sram_0 means that you have a peripheral attached to your tri-state bridge named "sram_0"... and in its PTF file entry, there is a non-shared write line specified.

- I think the confusion here is because of that separate SRAM interface, sram_0.... just remember that any signals for such interface are not for your chip (the HFCD1)...conversely, any signal (chipselect) with the name HFCE1 is a non-shared pin going to your device as specified.

- If other signals, such as the byte enables, are shared, then the 2-bit BE whose name is "ext_ram_bus..." is what you would connect to your custom SRAM interface.

Please let us know if you need any additional assistance.