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Altera_Forum
Honored Contributor
Honored ContributorExt flash connection in top level block diagram
For Altera Cyclone III (3c120) dev kit, I have the following connection for ext_flash in my verilog top level:- output [ 24: 0] top_fsa; : : wire [ 24: 0] top_fsa; wire [ 25: 0] ...
Altera_ForumHonored Contributor
Honored ContributorHi Cris72, thanks. But I wish to clarify your answer.
Did you mean draw 2 wires using 'Diagonal Bus Tool' and both also named as top_fsa[24..0]? Sorry it doesn't seem very clear to me.
