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Altera_Forum
Honored Contributor
Honored ContributorExt flash connection in top level block diagram
For Altera Cyclone III (3c120) dev kit, I have the following connection for ext_flash in my verilog top level:- output [ 24: 0] top_fsa; : : wire [ 24: 0] top_fsa; wire [ 25: 0] ...
Altera_ForumHonored Contributor
Honored ContributorDraw a bus wire from the sopc component port and leave it unconnected.
Double click it and rename it as: " top_fsa[24..0],dummy " Add another bus wire with both sides unconnected and name it top_fsa[24..0], then connect on side to an output pad symbol
