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Altera_Forum's avatar
Altera_Forum
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21 years ago

example designs

I've been benchmarking the example designs for the full-featured and the fast. Can anyone tell me what the reasoning was behind the choice of clock frequencies for the processors? If the cores are the same (both NIOS II/f) with the same caching, why not run the full-featured faster? Were there problems with the peripherals (like SDRAM?) that supported the choice of 50 MHz versus the 120 MHz input clock on the fast example? Another side note, why is the PLL set for 120 MHz and the SOPC builder set to 138 MHz? How does that work? I read the previous post about upping the clock on the 1S10 from 50 to 100 MHz and I'm trying that now. I hoped to not repeat the same steps to find the same problems others have already experienced. Thanks for the input.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    I never looked at the examples, but I do know the "s" core may have problems reaching 120Mhz due to the multiply/data shifting functionality.

    I've seen the SOPC builder select the wrong frequency before (seems to grab a clock value from the design, but why it would choose 138Mhz I'm not sure). A lot of the time it doesn't matter what the SOPC is built for unless there is a clock dependent core in the design (like a UART). However setting it properly is in your best interest since some pipelining optimizations are possible if you select the value properly.

    With the 1S10, if the design is not very busy you can probably reach 125Mhz (I think my fmax was 127Mhz), but go with sometime a bit less like 120 to give some breathing room. Other then that, if you understand how to create a design like the ref. designs then I think you shouldn't see any problems (test it with a software known to work like "hello world").

    Good-luck
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    I just checked all the example designs for the latest release (Nios II 1.0 SP1) and the PLL frequencies all match the system clock listed in SOPC Builder for that project. If they somehow got changed in your examples, it is incorrect. The PLL and SOPC Builder frequencies should match. Note that the fast design targeting the 1S40 board runs at 138MHz while the same design targeting the 1S10 runs at 120MHz. Perhaps this is the difference you noticed.

    The reason the full_featured example design has been set to a lower frequency than the fast design is that the full_featured design contains far more peripherals, which usually degrades the maximum frequency a system can run. In general, all other variables being the same, the more logic you add to a system, the slower it's maximum frequency will be.

    Hope that helps,

    -Nate
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

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    Thanks for the input and advice.

    --- Quote End ---

    I saw in the post:

    you were able to interface DE2 with TRDB_D5M and TRDB_LTM

    could you please share your vhdl code for interfacing the camera to the DE2 board or similar. I'm willing to pay you if its helpful.

    Please help me