Honored Contributor
Honored ContributorI've just considered 1bit async (each 'char' is 0x1) using a 4x clock.
A start bit sampled at t(0) might have happened just after t(-1) so the next transition might happen before t(3) or after t(4) - so we must not sample t(4n-1) or t(4n). t(1) and t(2) are the rest of the start bit - must be zero. t(5) and t(6) are the data, and must match. t(9) and t(10) are the stop bit, both must be 1. t(11) might be the start bit for the next character. Really shouldn't be that hard! I've just corrected the async format. Another uart spec I have uses 8, 16 or 32 times clock checking the middle 3 samples.
