Error probability UART RS232

I am using the uart corresponding http://www.alterawiki.com/wiki/fifoed_avalon_uart

My system clock has a frequency of 144 MHz, enough for sampling the serial line. Also, in my tests, it is achieved the maximum baud:

In the FPGA the elapsed time between receiving the first character until the last is 1250 ms, when I transmit 14400 characters in the computer.

(14400 characters * 10 bits/character) /115200 (bits/sec) = 1250 ms

The error in the status register comes when:

assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;

assign {stop_bit,raw_data_in,unused_start_bit} = rxd_shift_reg;

assign is_break = ~(|rxd_shift_reg);

assign is_framing_error = ~stop_bit && ~is_break;

always @(posedge clk or negedge reset_n)

begin

if (reset_n == 0)

unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= 0;

else if (clk_en)

unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;

end

assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in = (do_start_rx)? {10{1'b1}} :

(sample_enable)? {sync_rxd,

unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9 : 1]} :

unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;

assign rx_in_process = shift_reg_start_bit_n;

assign sample_enable = baud_clk_en && rx_in_process;

...

I suppose the error comes when a bit is out of sync, probably one of the last bit of the 10 sampled bits.