Error creating Project with custom component as reset and exception vector.

Hello,

I get the following error when creating a new NIOSII application and BSP from Template with a custom component as reset and exception vector for my NIOS/f cpu. See the attached picture for details.

Where my zim_qspi_controller components interfaces are set generic.

The generics are generated with the _hw.tcl scipt.

In the component the master communicates with a dual port fifo over the avs_mem interface.

--Speicher-Interface
		avs_mem_write			:in		std_logic;		
		avs_mem_waitrequest		:out	std_logic;
		avs_mem_read			:in 	std_logic;		    
		avs_mem_writedata		:in		std_logic_vector(AVALON_BUS_DATA_BYTES-1 downto 0);
		avs_mem_readdata		:out	std_logic_vector(AVALON_BUS_DATA_BYTES-1 downto 0);
		avs_mem_readdatavalid	:out	std_logic;
		avs_mem_byteenable		:in 	std_logic_vector(AVALON_BUS_DATA_BYTES/8-1 downto 0);
		--avs_mem_irq				:out	std_logic;	
		avs_mem_burstcount		:in		std_logic_vector (BURST_BTIS-1 downto 0);
		avs_mem_address			:in		std_logic_vector (ADDRESS_BITS-1 downto 0);

I am using:

Platform Designer 18.1 Build 625

NIOSII EDS 18.0.0.v20180425- 1